The present invention relates generally to integrated circuits. More particularly, embodiments of the invention relate to a method and apparatus for implementing trimming circuits.
Trimming circuits are used to configure and fine-tune IC products to meet final specification requirements. Such a trimming process typically occurs during the final stages of production. ICs are typically constructed with redundant circuit elements that are enabled or disabled by eliminating certain connections. The trimming process should reliably disengage undesired electrical connections while securely maintaining connections at other locations, as needed, for the lifetime of the product. Hereinafter, fuses are also referred to as trimming fuses.
One common method used for trimming involves intentional loading of certain metal structuresxe2x80x94fusesxe2x80x94with current well beyond the carrying capability of the fuse line. This results in vaporization of the metal and electrical discontinuity. Trimming is usually done on automatic testing machines using test programs that select the fuses to be eliminated. Fuse trimming is done by passing several hundred milliamps through the metal line. This instantaneously heats up the fuse to a high enough temperature so that it vaporizes within microseconds. Typically, the current passes to the fuse through a dedicated pad. Also, the external circuit can include a power supply with sufficient current carrying capability to eliminate several fuses at a time.
Partial trimming can result in a trimmed fuse that has a lower than acceptable residual resistance. This is undesirable after trimming and for the lifetime of the product because once this occurs the fuse can not be trimmed again. If the residual conductance is not high enough, sufficient current is unable to flow through the fuse and dissipate adequate heat to vaporize the residual conductive material.
Partial trimming of the fuse can be caused by power spikes during a turn-on transition of the power supply. Power spikes can result from the bouncing of relays that turn on the power supply. Power spikes can also result from power ringing within the power supply. Power ringing occurs during the turn-on transition as the circuit used to trim the fuse is closed and a large load is instantaneously realized.
Thus, there is a need for an improved trimming circuit. The circuit should remove power bouncing and voltage spiking during trimming. This circuit should also be capable of conducting sufficient current through the trimming fuse to efficiently break the connection with high residual resistance.
The present invention achieves the above needs with a method and circuitry for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long duration so as to decrease the switching speed of the transistor. The delay structure also provides a pass filter to filter power and voltage spikes in the select signal. Embodiments of the present invention enhance product yield by increasing the amount of IC products meeting specified performance requirements.
In one embodiment, the trimming circuit includes a delay structure that is designed into the gate of a transistor. In another embodiment, the trimming circuit includes a delay pad structure that is coupled between the first input pad and the gate of the transistor. In another embodiment, the trimming circuit includes a delay line structure coupled between the delay pad structure and the gate of the transistor. In other embodiments, the delay structure is designed into a combination of a gate of a transistor, an input pad, and a transmission line.
Another embodiment provides a delay transistor having a substrate, a plurality of conduction channels embedded in the substrate, and a plurality of active regions embedded in the substrate. The active regions alternate with the conduction channels to form source and drain portions of the delay transistor. Also included is a source contact coupled with first alternating active regions, a drain contact coupled with second alternating active regions, and a gate structure overlaying the conduction channels. The gate structure is configured to receive an input signal. The gate structure is a single gate structure. The gate structure has a serpentine shape to provide an RC delay to an input signal. The RC delay is of a sufficiently long duration so as to decrease the switching speed of the transistor. The RC attributes of the gate structure provide a pass filter to filter power and voltage spikes in the select signal.
Another embodiment provides a delay pad structure having a substrate and an active region embedded in the substrate. The active region is configured to receive an input signal. The active region has a serpentine shape to provide an RC delay to an input signal and to filter power and voltage spikes in the input signal. Also included is a plurality of diodes coupled with the active region. The diodes are reversed biased and provide additional capacitance to the RC delay.
Another embodiment provides a delay line structure having a substrate and a thin oxide layer coupled onto a first side of the substrate. Also, included is a polysilicon layer coupled onto the thin oxide layer. The polysilicon layer is configured to receive an input signal. The combination of the thin oxide layer coupled between the substrate and the polysilicon layer provide an RC delay to the input signal and to filter power and voltage spikes in the input signal. The thin oxide and polysilicon layers have a serpentine shape to provide additional RC delay to an input signal. Also, included is a plurality of diodes coupled with the polysilicon layer. The diodes are reversed biased and provide additional capacitance to the RC delay.